SDRAM

SDRAM
Synchronous dynamic random access memory.
synchronous means in sync with the input clock i.e its wait for the clock signal before responding to its controls input.
DRAM are asynchronous, which response as quickly as possible to change is control input.

CAS: column address strobe,referring to the column of the physical memory location in an array of capacitors used in DRAM module.
CAS Latency is the time that elapses after the memory controller sends a request to read a memory location and before the date is sent to the module's output pins.

Data is stored in individual memory cells, each uniquely identified by a memory bank, row and cloumn. To access DRAM, controller first select a memory bank, then a row(using RAS), then a cloumn(using CAS), and finally request to read the sata from physical memory location of the memory cell. The CAS lantecy is the number of clock cycles that elapes frm the time the request for data is sent to the actual memory location until the data is transmitted from the module.
Initialization of SDRAM:
Its initialized in a perdefined manner( Refer the data sheet of the choosen device). Operational procedures other than those specified may result in undefined operation.
Once power is applied to Vdd and Vddq(simultaneously) and the clock is stable( stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requries a 100us delay prior to issuing any command other than a COMMAND INHABIT or a NOP. Starting at some point during this 100us period and continuing at least through the end of this period, COMMAND INHABIT or NOP commands should be applied.
Once the 100us delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycle are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.

Commands
COMMAND INHIBIT: The COMMAND INHIBIT function prevents new commands from being excuted by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION(NOP): The NOP command is used to perform a NOP to an SDRAM which is selected. this prevents unwanted commands from being registered during idle or wait states.Operations already in progress are not afected.
ACTIVE: The ACTIVE command is used to open( or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1( bank select) inputs selects the bank and the address provided on inputs ( Address line) selects the row.This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
PRECHARGE: The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued.


...more command will be in next article.

my learning continous.......................Alim